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| PMC-Sierra,Inc. PM6344 EQUAD * Supports Line and Path performance monitoring according to ITU recommendations. Accumulators are provided for counting CRC-4 errors, Far-End Block Errors (FEBEs), frame sync errors, and Line Code Violations (LCVs). * Extracts the datalink. Extracts selected channels. * Provides a 2-frame elastic store buffer for jitter and wander attenuation. timeslot 16 AIS, remote alarm, and remote multiframe alarm. * Provides a digital PLL for generation of a low jitter transmit clock. * Provides a FIFO buffer for jitter attenuation and transmit rate conversion. FIFO full or empty indication allows for bit-stuffing in higher rate multiplexing applications. Quad E1 Framer FEATURES * Monolithic single-chip device which integrates four full-featured E1 framers and transmitters for terminating duplex E1 signals. * Frames to a G.704 2.048 Mbit/s signal. Frames to the signalling multiframe and to the CRC multiframe when enabled. * Supports HDB3 or AMI line codes. * Supports transfer of PCM and signalling data to/from 2.048 Mbit/s or 16.384 Mbit/s backplane buses. Supports n DS0 backplane interface for fractional E1. * Provides Channel-Associated Signalling (CAS) extraction/insertion, programmable idle and digital milliwatt code substitution, and up to three multiframes of signalling debounce on a per-channel basis. * Provides trunk conditioning which forces programmable trouble code substitution and signalling conditioning on all/selected channels. * Provides an HDLC interface for terminating/generating a datalink. * Optionally extracts the datalink from timeslot 16 or from any combination of the national bits. * Software and functionally compatible with the PM6341 E1XC Single E1 Transceiver. Pin-compatible with the PM4344 TQUAD Quad T1 Framer. * Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring. * Low power 5 V CMOS technology. * Available in a rectangular 128-pin PQFP (14 by 20 mm) package. APPLICATIONS * E1/E3 Multiplexers and Digital Private Branch Exchanges (PBXs) * E1 Frame Relay Interfaces * E1 ATM Interfaces * Fractional E1 Interfaces * Digital Access and Cross-Connect Systems (DACS) and Electronic DSX Cross-Connect Systems (EDSXs) * Digital Loop Carriers (DLCs) * E1 Channel Service Units (CSUs) and Data Service Units (DSUs) * ISDN Primary Rate Interfaces (PRI) * SDH Add/Drop Multiplexers (ADMs) TRANSMIT SECTION * Optionally accepts/provides dual-rail digital PCM inputs/outputs. * Formats data to create a G.704 2.048 Mbit/s signal. Optionally inserts signalling multiframe alignment signal. Optionally inserts CRC multiframe structure including optional transmission of FEBEs. * Allows insertion of a datalink. Allows insertion of selected channels through a serial port. * Supports transmission of the AIS, BLOCK DIAGRAM TCLKI[1:4] BTPCM/BTDP[1:4]/MTD* BTSIG/BTDN[1:4] BTFP[1:4]/MTFP* BTCLK[1:4]/MTCLK* BTIF Backplane Transmit Interface TOPS Timing Options DJAT Digital Jitter Attenuator Transmitter DTIF Digital Transmit Interface TCLKO[1:4] TDP/TDD[1:4] TDN/TFLG[1:4] TDLCLK/TDLUDR[1:4] TDLSIG/TDLINT[1:4] XBAS Basic Transmitter: Frame Generation, Alarm Insertion, Trunk Conditioning, Line Coding PCSC Per-channel Controller: Signalling, Idle Insert XFDL HDLC Transmitter BRCLK*/MRCLK* BRFPI*/MRFPI* MENB* PMON Performance Monitor Counters DRIF DS-1 Receive Interface CDRC Clock and Data Recovery FRMR Framer: Frame Alignment, Alarm Detection ELST Elastic Store SIGX Signalling Extractor, Trunk Condition Receiver BRPCM/BRDP[1:4] BRSIG/BRDN[1:4] BRFPO[1:4] BRIF Backplane Receive Interface RECEIVE SECTION * Recovers clock and data using a digital PLL for high jitter tolerance. * Accepts/provides dual- or single-rail digital PCM inputs/outputs. Accepts gapped data streams to support higher rate demultiplexing. * Provides Loss Of Signal (LOS) detection, and indicates loss of frame alignment (OOF), loss of signalling multiframe, and loss of CRC multiframe. Indicates reception of remote alarm, remote multiframe alarm, Alarm Indication Signal (AIS) and timeslot 16 AIS. PMC-950510 (R6) XCLK/VCLK* RCLK[1:4] RDP/RDD[1:4] RDN/RLCV[1:4] MRD* RCLKO[1:4] Internal Bus A[9:0]* RDB* WRB* CSB* ALE* INTB* RSTB* D[7:0]* DJAT Digital Jitter Attenuator Optional Placement RFP[1:4] MPIF Microprocessor Interface RFDL HDLC Receiver RDLSIG/RDLINT[1:4] RDLCLK/RDLEOM[1:4] * These signals are shared between all eight framers. - - - Optional connections are shown with dashed lines. a 1998 PMC-Sierra, Inc. October, 1998 PM6344 EQUAD Quad E1 Framer TYPICAL APPLICATIONS FULLY CHANNELIZED HDLC APPLICATION Processor PM4314 QDSX QUAD T1/E1 LIU PM6344 EQUAD Quad E1 Framer PM4344 TQUAD Quad T1 Framer PM7366 FREEDM-8TM Frame Engine and Datalink Manager 4 Packet Memory PCI Bus STRUCTURED / UNSTRUCTURED E1 AAL1 OCTAL PORT CARD 4 PM4314 QDSX Quad T1/E1 LIU PM6344 EQUAD Quad E1 Framer PM73121 AAL1gator IITM AAL1 SAR Processor 4 PM4314 QDSX Quad T1/E1 LIU PM6344 EQUAD Quad E1 Framer UTOPIA Bus Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-950510 (R6) a 1998 PMC-Sierra, Inc. October, 1998 AAL1gator II and FREEDM-8 are trademarks of PMC-Sierra, Inc. |
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